1. Field of the Invention
The present invention relates to a method of displaying a result of a logic simulation performed to examine suitability on the design of logic circuits, and a logic simulation support equipment capable of displaying the result of the logic simulation.
2. Description of the Related Art
In recent years, a digital equipment such as a digital computer composed of logic circuits including a printed circuit board and an application specified integrated circuit (ASIC) and the like has increasingly become a large scale and complex system. Generally, the logic simulation is performed in order to examine the suitability of designed logic circuits on the design stage before mass-producing such a digital equipment.
The logic simulation result is displayed on a CRT, etc. While viewing the display, the operator confirms the operation of the logic circuits and finds malfunctions, etc. In such a case, signal waveforms as shown in FIG. 23 and Fig, 24 are displayed as the logic simulation result.
In an example shown in FIG. 23, signal waveforms are displayed as the logic simulation result obtained in a simulation display time interval .DELTA.T (=T3-T0) that was set in advance from a display start time T0. In the conventional display system, output waveforms of specific signals (XAS, XRV) as well as a clock signal (CLK) are displayed on all the points observed in the interval from time T0 to T3.
And, a part of the display shown in FIG. 23 is expanded as shown in FIG. 24 as needed. In an example shown in FIG. 24, the output waveforms are displayed to be expanded in a time interval from time T1 through T2 out of the display shown in FIG. 23. Also in this case, all the points observed in the interval from time T1 to T2 are displayed.
Incidentally, accompanied with large integration of logic circuits in recent years, the analysis of a malfunction requires an enormously long time, when a malfunction is found during the operational confirmation of logic circuits on a design stage. Accordingly, it has been requested to facilitate the operational confirmation of logic circuits and the analysis of malfunctions.
When the operational confirmation of logic circuits and the analysis of malfunctions are performed while referring to a logic simulation result displayed, signal waveforms are expanded or reduced on the display as shown in FIG. 23 and FIG. 24. When finding a malfunction of the logic circuits and analyzing the malfunction, generally the operator refers to the total display of the logic simulation result on the screen. After finding a part having the possibility of a malfunction, the operator refers to a detailed signal value of the part and judges whether or not a malfunction occurs in the part, and in addition, analyzes the malfunction if a malfunction occurs.
Thus, when finding a malfunction of logic circuits from a logic simulation result and analyzing the malfunction, the operator repeats expanding and reducing the display of signal waveforms on one window so as to grasp both the total picture and the detailed parts of the logic simulation result. Expanding and reducing the display on one window in this manner, the operator will break thinking each time when a window display is switched, which lowers efficiency of the work to analyze.
Accordingly, in the technique disclosed in the Japanese Patent Application Laid Open (KOKAI) No. Hei 7 (1995)-287721, a plurality of pairs of display start time and display time interval are set in advance, and signal data corresponding to the display start time and display time interval are each displayed in a plurality of display regions on the display (CRT display unit). According to this technique, the operator can refer to a reduced picture to display the total logic simulation result and a detailed (expanded) picture in a certain time interval on one screen at the same time. Therefore, the operator does not need to break thinking and can easily continue the work to analyze.
However, in the technique disclosed in the foregoing patent application, a time setting file in which the display start time and display time interval for designating a display time are preset has to be made, and the operator cannot optionally designate and change a display start time and display time interval while referring to a logic simulation result.
Further, in the same patent application, as shown in FIG. 23 and FIG. 24, output waveforms as a logic simulation result are displayed on all the points observed through a display time interval from a display start time; and therefore, especially when an extended logic simulation result is displayed, the total picture cannot effectively be displayed on one screen. Consequent y, the operator cannot easily grasp the total logic simulation result, which invites inefficiency of the work to analyze.